Bearwood Engineering was founded by Kelly Stephens in 2007 after a career spent in the field of Integrated Circuit design. After graduating from Rose-Hulman Institute of Technology in 1988, my career started with Motorola, Inc. in the Semiconductor Product Sector. At that time, Motorola SPS was the world's second largest manufacturer of semiconductors. After thirteen years at Motorola, the second half of my career as a direct hire was spent with ELMOS Semiconductor AG.
While the first three years with Motorola were spent in Arizona, the bulk of the time was spent at a small design center in Kokomo, Indiana. The site was a joint venture between Motorola and Delco Electronics (now Delphi Automotive).
The Integrated Circuits developed at the “Joint Design Center” were all micro-controller based and intended for Automotive applications. Over the years, several powertrain controllers were developed for General Motors using the 68000 micro-processor core. A family of Anti-Lock Brake (ABS) controllers were also design utilizing the HC11 core.
Around these CPU cores a variety of standard and custom modules were developed. The custom work involved specification, design, test and debug of communication protocols, sensor interfaces, and control functions.
Design of these integrated circuits was performed cooperatively by engineers from both Motorola and Delco Electronics. Consequently, the design tools utilized were a mixed bag from both companies and required additional on-site tool integration support that was not provided by the home offices.
Commonly we needed to translate from one netlist format to another. As we were utilizing two well defined flows the number of different formats involved was constant and the number of translations needed small. In this environment, the translators developed converted directly between dissimilar formats.
At the time, DRC and LVS physical verification was time consuming often requiring tens of hours for a complete battery of tests. As final tape-out approaches the edits needed to complete the pristine design become less intrusive and involve fewer layers. To accelerate the process a modular set of DRC and LVS routines was developed to selectively run rule subsets or module subsets to check affected layers and circuits. This allowed the modify-verify loop to be compressed and improved the certainty of meeting tape-out deadlines.
In the mixed tool environment, enhancements to the 'make' based development tools were implemented which simplified the integration of modules from dissimilar tools and intelligently managed dependancies, revisions and selection of different modelling levels (behavioral, stub, gate-level, etc).
In the drive to reduce module size, bumped flip-chips were utilized for several of the later projects. In these cases the challenge was to find a substitute replacement for final part test and guarantee Known-Good-Die. Our solution was to implement wafer-level burn-in. Much of the required burn-in circuitry was implemented on wafer with sacrificial components. This circuitry was fabricated with a 1x wafer mask. Manually drafting the data required to produce these mask proved to be problematic. This lead me to develop a tool to generate layout data under script control.
Once the tool was available, it quickly found additional applications. Pad ring generation was one such use. We found that changing the footprint of a chip required a large amount of rework. With pad ring generation, shifting and rearranging pads became a trivial operation. The scripting tool would place the pad cells and generate the inter pad cell “stitching.”
At the turn of the century/millennium Motorola began closing many of its satellite design centers and pulling personnel back to central design hubs. After refusing several requests to move to Austin, Motorola finally closed our design center. Rather than going our separate ways, my team elected to find another company that would like to establish a design center in Kokomo. ELMOS Semiconductor AG, with its automotive focus was a perfect match. At ELMOS, our experience with micro-controller ASICs was a timely asset for a new North American design project. During our tenure with ELMOS, we also participated on several designs without CPU cores.
In the ongoing pursuit of perfection or Zero-PPM persistent causes of failures are analyzed and eliminated. One cause of failure is insufficient data retention in non-volatile memory (NVM). While development of a bit cell that is 100% reliable is a worthy goal it is also unrealizable. In parallel to the development of a better cell, designing an array that is tolerant of faulty bits provides and immediate boost in product quality. One common approach is the use of redundant bits to store error correction codes (ECC) allowing for recovery of the original data.
Fallout can be further reduced through improved test coverage. The development of sophisticated test algorithms of non-volatile memory was a major activity for one of our products.
At ELMOS, I also had several opportunities to create PC based GUI programs for the evaluation of the ASICs developed. The evaluation software was capable of fully exercising the devices for proof of concept and also capable of performing Failure Analysis of returned defective product.
As the years rolled on, calls to relocate to the central office began to arise. In the end, we did relocate our local team to the North American Headquarters in Farmington Hills, MI. It only took a year for me to remember what I had realized in three years in Phoenix: I am not a big city guy. I then left Michigan and returned to my home town to start my own business. My relationship with ELMOS was not severed and I continued to work on their projects while developing a tool that could be released to the general market...